Product Summary

The epm240t100c5n instant-on, non-volatile CPLD is based on a 0.18-μm, 6-layermetal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. The epm240t100c5n offers high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP). The epm240t100c5n is designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.

Parametrics

epm240t100c5n absolute maximum ratings: (1)Internal supply voltage: –0.5 to 4.6 V With respect to ground; (2)I/O supply voltage: –0.5 to 4.6 V; (3)DC input voltage: –0.5 to 4.6 V; (4)DC output current, per pin: –25 to 25 mA; (5)Storage temperature: –65 to 150 ℃ at No bias; (6)Ambient temperature: –65 to 135 ℃ at Under bias; (7)Junction temperature: 135 ℃ at TQFP and BGA packages under bias.

Features

epm240t100c5n features: (1)Low-cost, low-power CPLD; (2)Instant-on, non-volatile architecture; (3)Standby current as low as 29 μA; (4)Provides fast propagation delay and clock-to-output times; (5)Provides four global clocks with two clocks available per logic array block (LAB); (6)UFM block up to 8 Kbits for non-volatile storage; (7)MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V; (8)MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels; (9)Bus-friendly architecture including programmable slew rate, drive strength, bushold, and programmable pull-up resistors; (10)Schmitt triggers enabling noise tolerant inputs (programmable per pin); (11)I/Os are fully compliant with the Peripheral Component Interconnect Special; (12)Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V; (13)operation at 66 MHz; (14)Supports hot-socketing; (15)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (17)ISP circuitry compliant with IEEE Std. 1532.

Diagrams

epm240t100c5n block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
EPM240T100C5N
EPM240T100C5N


IC MAX II CPLD 240 LE 100-TQFP

Data Sheet

0-1: $3.60
Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
EPM2210F256C3
EPM2210F256C3


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-1: $41.91
EPM2210F256C3N
EPM2210F256C3N


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-1: $38.10
EPM2210F256C4
EPM2210F256C4


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-90: $29.30
EPM2210F256C4N
EPM2210F256C4N


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-1: $26.64
EPM2210F256C5
EPM2210F256C5


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-1: $20.92
EPM2210F256C5N
EPM2210F256C5N


IC MAX II CPLD 2210 LE 256-FBGA

Data Sheet

0-1: $19.02